1. Field of the Invention
The present invention relates to the design of circuits that operate asynchronously. More specifically, the present invention relates to an asynchronous control circuit with symmetric forward and reverse latencies.
2. Related Art
As computer system clock speeds become progressively faster, it is becoming increasingly harder to synchronize the actions of computer system components with reference to a centralized system clock. To deal with this problem, computer system designers are beginning to investigate the use of asynchronous circuits that operate in a self-timed manner, without having to adhere to the constraints imposed by a centralized system clock.
Asynchronous circuits often make use of “control queues” to coordinate the movement of data between asynchronously controlled latches. Note that a control queue can be constructed using GasP modules, see “GasP: A minimal FIFO control,” by Ivan Sutherland and Scott Fairbanks, Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46-53, IEEE Computer Society Press, March 2001. See also, U.S. Pat. No. 5,937,177 to Molnar and Fairbanks and U.S. Pat. No. 6,356,117 to Sutherland, et al. concerning asP* and GasP circuits, respectively.
For example, FIG. 1A illustrates a three-module control queue built with 4-2 GasP modules, which has an item latency in the forward direction of four delay units per module and a reverse latency of two units per module. This control queue forwards input control signals ui and li to produce output control signals uo and lo, where the items flow from left to right through the queue, and the acknowledge signals that introduce bubbles into the queue flow from right to left. At the input interface, ui and li are mutually exclusive, and either ui or li is acknowledged by an ai. The corresponding output interface acknowledge signal is ao. In this configuration, the item flow from left-to-right is subject to four delay units per module while the bubble flow from right-to-left is subject to two delay units per module.
Each of these control queue modules is known as a decision-wait module and can be constructed from a pair of GasP Join modules as is illustrated in FIG. 1B. The join module performs the “last of” function, where it generates one or more output signals (it fires) after the last of all of its input signals have been received. Upon firing, it also resets all its input signals. Input signals of the join are indicated by a small triangle, and when this triangle is filled in, it indicates that an initial condition where that input has already been received. In FIG. 1B, the common input c of decision-wait module 104 is coupled to the reverse-going inputs of both Join modules, so that when one fires, it reneges on the reverse-going input of the other Join module. The XOR function required to produce the common input interface acknowledge signal cc is achieved by wire-ORing a reverse-going output from each join module. Either join module firing will generate an acknowledge signal cc.
A decision-wait module is well known in the field of asynchronous design. FIG. 2 illustrates a 2×1 decision wait-module 202. As illustrated in FIG. 2, 2×1 decision-wait module 202 has two mutually exclusive inputs, a0 and a1, one common input, b, and two outputs, c0 and c1. Upon receipt of one of the mutually exclusive input signals a0 or a1 and the common input signal b, decision-wait module 202 generates a single output, either c0 or c1 dependent on which of the mutually inputs was received:                a0 and b generates c0,        a1 and b generates c1.Decision wait modules can be cascaded to form control signal queues as shown in FIGS. 1 and 3.        
FIG. 3A illustrates an alternative scheme for building a control queue using 2-4 GasP modules. In this scheme, the control signal travel is in the reverse direction through the queue from left to right. This results in an item latency of two delay units per module from left to right and a bubble latency of four delay units per module from right to left.
FIG. 3B illustrates how a decision-wait module 304 can similarly be constructed from a pair of GasP join modules. As illustrated in FIG. 3B, the common input c of decision-wait module 304 is coupled to the reverse-going inputs of both Join modules, so that when one fires, it reneges on the reserve-going input of the other Join module. The XOR function required to produce the common input interface acknowledge signal cc is achieved by wire-ORing a reverse-going output from each join module. Either join module firing will generate an acknowledge signal cc.
Control queues and FIFOs that have a longer forward latency and shorter reverse latency tend to be used in application where it is desirable to operate in a mode where the queue or FIFO is more than half full. They also offer better matching between control and data flow in FIFOs: a bundling constraint is that control must never progress ahead of its associated data. Control circuits that have less forward latency and longer reverse latency are often favored in applications where queues or FIFOs are operating closer to empty and thus each item input will propagate more quickly to the output. However, it is often difficult to match such control to the movement of data in a FIFO because the data movement tends to be the limiting delay in forward latency.
Each of the above described control queues can be useful for certain applications that have different latency requirements for item flow and bubble flow. However, in some applications it is desirable to provide equal latency for item flow and bubble flow. Hence, what is needed, is an apparatus and a method that facilitates controlling an asynchronous circuit using a control queue with equal item flow and bubble flow latencies.